1. Field of the Invention
Exemplary embodiments of the present invention relate to a semiconductor memory device and method for operating the same, and more particularly, to a semiconductor memory device including a mode register set.
2. Description of the Related Art
A register set (RS) is generally used for an operation of setting a particular mode among the operations of a Dynamic Random Access Memory (DRAM) device. Examples of an RS include a mode register set (MRS) and an extended mode register set (EMRS).
The MRS and EMRS set the DRAM device at a particular operation mode based on an MRS code applied through an address pin along with a mode register set command, and the established mode is maintained until a power source is no longer applied to the semiconductor memory device.
FIG. 1 is a block view illustrating an MRS command generation circuit of a known semiconductor memory device.
Referring to FIG. 1, the MRS command generation circuit includes an MRS mode signal generator 110, an address buffer 120, an MRS selection signal generator 130, and a plurality of MRS command generators 150A to 150E.
The MRS mode signal generator 110 may generate an MRS mode signal MRSP by decoding external command signals /CS, /RAS, /CAS and /WE. In particular, the MRS mode signal generator 110 may generate an MRS mode signal MRSP having the same pulse width as the pulse width of a clock signal CLK. The MRS mode signal MRSP may be enabled in an MRS mode where all the external command signals /CS, /RAS, /CAS and /WE are in a logic low level.
The address buffer 120 may output MRS source signals MREGI<0:12> for generating a plurality of MRS commands NMRS_CMD<0:12>, EMRS_CMD<0:12>, EMRS2_CMD<0:12>, EMRS3_CMD<0:12> and TMRS_CMD<0:12> based on first MRS codes A<0:12> applied through address pins A0 to A12 included therein in response to the enabled MRS mode signal MRSP.
The MRS selection signal generator 130 may generate a plurality of MRS selection signals NMRSP, EMRSP, EMRSP2, EMRSP3 and TMRSP for selecting an MRS mode to be set based on second MRS codes BA<0:2> applied through bank address pins B0 to B2 in response to the enabled MRS mode signal MRSP.
The MRS selection signal generator 130, as shown in the following Table 1, generates a plurality of MRS selection signals NMRSP, EMRS, EMRS2, and EMRS3 for setting an extended mode register by logically combining and decoding the logic values of the second MRS codes BA<0:2> that are applied to the bank address pins B0 to B2, and generates a TMRS selection signal TMRS for a test mode setting command based on the logic value of an MRS code A<7> which is applied to the seventh address pin A7.
TABLE 1NMRSEMRSEMRS2EMRS3TMRSA<7>0Do not careDo not careDo not care1BA<0>01010BA<1>00110BA<2>00000
The MRS command generators 150A to 150E may generate the MRS commands NMRS_CMD<0:12>, EMRS_CMD<0:12>, EMRS2_CMD<0:12>, EMRS3_CMD<0:12> and TMRS_CMD<0:12> for setting the MRS mode of the semiconductor memory device by logically combining and decoding the MRS source signals MREGI<0:12> and the MRS selection signals NMRSP, EMRSP, EMRSP2, EMRSP3 and TMRSP.
To this end, the MRS command generators 150A to 150E may include an NMRS command generator 150A, an EMRS command generator 150B, an EMRS2 command generator 150C, an EMRS3 command generator 150D, and a TMRS command generator 150E.
The NMRS commands NMRS_CMD<0:12> include commands for setting NMRS based on the Joint Electron Device Engineering Council (JEDEC) specification of 512 MB Double Data Rate 2 Synchronous Dynamic Random Access Memory (DDR2 SDRAM) presented in FIG. 2.
FIG. 2 shows commands based on the JEDEC specification of a 512 MB DDR2 SDRAM device.
The NMRS commands NMRS_CMD for setting the NMRS include codes for setting a burst length, a burst type, an operation mode, and a CAS latency. Also, address pins are assigned for the setup of the codes.
For example, address pins A0 to A2 are assigned for setting up the burst length, and an address pin A3 is assigned for setting up the burst type BT. Address pins A4 to A6 are assigned for setting up the CAS latency, and address pins A7 to A12 are assigned for receiving an MRS code, including a test mode code TM, a DLL reset code DLL, a write recovery code WR, and a power down code PD, for setting up the operation mode.
Meanwhile, since MRS is set up through the address pins, the modes that are not included in the address pins A0 to A12 are set through an EMRS. The EMRS commands EMRS_CMD may include several commands for setting EMRS, and the EMRS2 commands EMRS2_CMD and the EMRS3 commands EMRS3_CMD may include several commands for setting the EMRS2 and the EMRS3, respectively.
However, because the NMRS command generator 150A, the EMRS command generator 150B, the EMRS2 command generator 150C, the EMRS3 command generator 150D, and the TMRS command generator 150E, in accordance with the known technology, have to receive MRS codes through the address pins A0 to A12 that are already provided, the MRS command generators 150A to 150E are formed in a peripheral circuit region. For this reason, the density of the peripheral circuit region becomes high and the size of the peripheral circuit region becomes great, creating a disadvantage in terms of design efficiency.
The MRS commands NMRS_CMD<0:12>, EMRS_CMD<0:12>, EMRS2_CMD<0:12>, EMRS3_CMD<0:12> and TMRS_CMD<0:12>, which are generated in the MRS command generators 150A to 150E disposed in the peripheral circuit region, have to be transferred from the peripheral circuit region to the constituent elements where the MRS commands are used inside of a semiconductor memory block. Therefore, data lines extending from the peripheral circuit region to the constituent elements where the MRS commands are used inside of a semiconductor memory block are required to transfer the MRS commands NMRS_CMD<0:12>, EMRS_CMD<0:12>, EMRS2_CMD<0:12>, EMRS3_CMD<0:12> and TMRS_CMD<0:12>.
Recently, as the number of modes set in a semiconductor memory device increases, the number of MRS codes increases as well. Since it is expected that more address pins need to be assigned to receive more MRS codes, the size of the semiconductor memory device is expected to increase, which leads to a decrease in cell capacity.
Also, according to the known technology, whenever the first MRS codes A<0:12> and the second MRS codes BA<0:2> are sequentially inputted through the address pins, they should be decoded, which is vexatious. The decoding process not only deteriorates the driving rate of the semiconductor memory device, but also increases the amount of power consumption. The more times the decoding process is performed, the more power is consumed.